Certain micro-controllers have been optimised for use in applications where power consumption is an important consideration, as will normally be the case when equipment is to be battery powered. A micro-controller will typically be at the center of a control system for such equipment, and if the power demand of the control system itself can be reduced, then the time for which the equipment may remain powered by a battery is correspondingly extended.
One technique for reducing the power demand of a micro-controller is to allow parts of the micro-controller to be disabled or even switched off entirely when they are not required to perform a control function. For example, if the equipment is in a stable state and it is known that no control parameters will need to be accessed or modified for some time, then the relatively power hungry memory access circuitry associated with the micro-controller may be powered down until needed. Similarly, the computational parts of the micro-controller circuitry may be powered down. Another technique for reducing power demand is by slowing down the operation of the micro-controller. Since data storage within semi-conductor devices is essentially a charge storage mechanism and data manipulation involves charging or discharging the storage nodes then clearly less energy is consumed if a micro-controller can be clocked more slowly and yet still provide the required control parameters in time, as again may be the case if the controlled equipment is currently stable.
The types of power saving measures described above have become known as putting all or parts of the micro-controller circuitry to sleep, and power optimisable micro-controllers having a variety of sleep modes have become available. The modes may include, a partial disabling or slowing of circuitry and indeed switching off circuitry all together (deep sleep). An advanced micro-controller may have circuitry blocks each of which is fed by a different clock, which therefore comprises a controller with different clock domains. These domains may be separately placed in the available sleep modes as the application permits.
The clocks for the various domains may be derived from a single oscillator and gated through to the different domains or in some designs a dedicated oscillator may feed a single domain. Thus in some applications it may be possible to consider switching off the oscillator all together as a way of saving even more power than just disabling a clock domain. Whether this is possible will depend to a large extent on the time taken by the oscillator to turn back on and stabilise, since clearly the restart period represents the minimum time for which such a deep sleep mode by be entered. If the time taken for an oscillator to restart and stabilise can be reduced, then the deep sleep mode may potentially be entered more often with a consequent advantageous power saving.
A typical approach to providing an oscillator is to take a circuit configuration that is unstable and therefore capable of oscillation. Oscillation is started by allow the arrangement to amplify noise within the circuit. U.S. Pat. No. 5,923,222 to Motorola shows that start-up may be improved if suitable initial conditions within the normal operating range of the circuit are provided prior to noise amplification and United States Patent Application Published under number 2002/167364 recommends applying as initial input conditions for one stage of a ring oscillator levels that would be encountered once normal oscillation had commenced.